Semiconductor practitioners are continuously working toward improved performance of semiconductor devices and/or the process of fabricating semiconductor devices. It is well known that silicides are one way to provide electrical contacts in semiconductor devices. The characteristics of contact silicides in n-type field effect transistors (nFETs) and p-type FETs (pFETs) in turn affect performance characteristics, such as contact resistance and differences between on and off currents. However, in the existing integrated circuit having both nFETs and pFETs with silicide contacts, the performances of the nFETs and pFETs are not imbalanced, especially when the nFETs and pFETs utilize different semiconductor materials. This leads to the difficulty of process integration that causes the degradations of the integrated circuit, including higher contact resistances of the source/drain in the pFETs for example.
Therefore, what is needed is the structure and the method masking the same to address the above issues.